1. Field of the Invention
This invention relates to a driving circuit for driving a liquid crystal display device, in particular, a signal line driving circuit.
2. Description of the Related Art
FIG. 2 shows an example of an active matrix type liquid crystal display device in which analog gradation lines are driven sequentially. The active matrix type liquid crystal display device includes a pixel matrix portion 200, a signal line driving circuit 240 and a scanning line driving circuit 250.
In the pixel matrix portion 200, signal lines 201 to 203 and scanning lines 204 to 206 are arranged at a matrix form. Pixel thin film transistors (TFTs) 207 to 210 are arranged in intersection portions of the signal lines and the scanning lines. In each of the TFTs 207 to 210, a gate, a source and a drain are connected with the scanning line, the signal line and a pixel electrode, respectively. In general, since a capacitance of liquid crystals 211 to 214 arranged between the pixel electrodes and opposite electrodes cannot have a large value, storage capacitors 215 to 218 for storing charges are arranged in vicinity of the pixel electrodes.
When a voltage higher than a threshold voltage of the TFT is applied to the scanning line and the TFT is turned on, the drain and the source in the TFT are in a short circuit state. When a voltage on the signal line is applied to the pixel electrode, the liquid crystal and the storage capacitor are charged. On the other hand, when the TFT is turned off, since the drain and the source is in an open circuit state, charges in the liquid crystal and the storage capacitor are stored until the TFT is turned on.
FIG. 3 shows an example of the signal line driving circuit 240. The signal line driving circuit 240 includes a shift register circuit 350, a buffer circuit 351, a sampling circuit 352, a transfer circuit 354 and an analog buffer circuit 353. The shift register circuit 350 has flip-flops (F/Fs) 330 to 332. The buffer circuit 351 has invertor type buffers 308 to 313. The sampling circuit 352 has switches 314 to 316 and storage capacitors 317 to 319. The transfer circuit 354 has switches 320 to 322. The analog buffer circuit 353 has analog buffers 340 to 342 and storage capacitors 323 to 325.
In an analog gradation, a continuous video signal is used as a gradation signal input to the signal line driving circuit 240. When a liquid crystal is a normal white mode, it is set that a display portion of the liquid crystal display device approaches black in accordance with increase of an absolute value of a voltage applied to the liquid crystal. The video signal is input from a video signal input terminal 303. A start pulse signal which synchronizes the video signal is input from a start pulse signal input terminal 302 to a flip-flop 330 of the shift register circuit 350, and then the shift register circuit 350 is shift-operated in response to a clock pulse signal input from a clock pulse signal input terminal 301. An output of the flip-flop 330 of the shift register circuit 350 is input to the switch 314 of the sampling circuit 352 through the buffers 308 and 309 of the buffer circuit 351.
FIG. 4 shows an example of a transmission gate in which an N-channel TFT and a P-channel TFT are combined. The transmission gate includes a control terminal 401, an input terminal 402, an output terminal 403, an N-channel TFT 405 and a P-channel TFT 404. In FIG. 4, the input terminal 402 is electrically connected with the video signal line 360 and the output terminal 403 is electrically connected with the capacitor 317 or the like. Each of the switches 314 to 316 in the sampling circuit 352 is constructed by the transmission gate. The transmission gate is turned on/off by the buffer circuit 351 through the control terminal 401.
When the switch 314 is turned on, the video signal line 360 is electrically connected with the storage capacitors 317 to 319 of the sampling circuit 352 to store charges in the capacitors 317 to 319. When the start pulse signal passes through the flip-flop 330, an output of the flip-flop 330 is reversed, the switch 314 is turned off.
Since charges are stored in the storage capacitor 317, a voltage is stored until the switch 314 is turned on. After sampling of one line is completed, a transfer signal is input from a transfer signal input terminal 304 before next sampling is started. Therefore, the switches 320 to 322 of the transfer circuit 354 are turned on, the storage capacitors 317 to 319 are electrically connected with the storage capacitors 323 to 325 of the analog buffer circuit 353 to store a voltage in the capacitors 323 to 325.
When a capacitance value of the capacitors 323 to 325 is sufficiently smaller than that of the capacitors 317 to 319 and when the capacitors 317 to 319 and the capacitors 323 to 325 are in a short circuit state, change of the voltage is small. When the switches 320 to 322 are turned off, the voltage is stored in the storage capacitors 323 to 325.
The analog buffers 340 to 342 of the analog buffer circuit 353 are connected with the storage capacitors 323 to 325 to drive the signal lines through the analog buffers 340 to 342. The analog buffer circuit 353 is necessary to drive the signal lines without influencing the voltage of the storage capacitor.
FIGS. 5A shows an example of the scanning line driving circuit 250. The scanning line driving circuit 250 includes clocked invertor used circuits 510 to 512 (as shown in FIGS. 5B), NAND circuits 503 and 504 and invertor type buffers 505 and 506. The clocked invertor used circuit includes clocked invertors 520 and 521 operated by a clock signal CK (as shown in FIG. 5C) and an invertor 522. The start pulse signal which synchronizes a vertical synchronizing signal is input from a start pulse signal input terminal 502, and the clock pulse signal which synchronizes a horizontal synchronizing signal is input from a clock pulse signal input terminal 501. Therefore, the scanning lines are driven sequentially through scanning line connection terminals 507 and 508.
In a conventional signal line driving circuit, as described above, an analog switch such as the transmission gate is used in a sampling circuit. It is necessary to operate the sampling circuit at high speed. Also, it is desired that a TFT to be used has performances such as high mobility and a small capacity. However, these characteristics contrast with a characteristic such as a withstanding voltage of the TFT. That is, if the withstanding voltage is improved, since a high speed performance deteriorates, the TFT cannot be operated at high speed.
FIG. 6 shows a conventional sampling circuit. The sampling circuit includes a switch 601, a storage capacitor 602, a gradation signal input terminal 603, a storage capacitor connection terminal 604, and a control signal input terminal 605. FIGS. 7A to 7C show voltage waveforms in the gradation signal input terminal 603, the storage capacitor connection terminal 604 and the control signal input terminal 605, respectively. If a direct current (DC) voltage is applied to a liquid crystal for a long period of time, a characteristic of the liquid crystal deteriorates. Therefore, an alternating current (AC) voltage as shown in FIG. 7A is applied to the liquid crystal.
The AC voltage having 14 V (peak to peak) is applied from the gradation signal input terminal 603. A pulse signal as shown in FIG. 7C is applied to the control signal input terminal 605. When the pulse signal is high, sampling is performed and the AC voltage is applied to the storage capacitor 602. When the pulse signal is low, the switch 601 is opened and charges are stored in the storage capacitor 602 until next sampling is started. Since a voltage having the same amplitude as the AC voltage may be applied between the gradation signal input terminal 603 and the storage capacitor connection terminal 604, it is required that the TFT constructing the switch 601 withstands the AC voltage, thereby to deteriorate a high speed performance.